During microprocessor operation, every memory access must go through an address translation process before the data can be fetched from or written to the memory subsystem. Block Address Translation (BAT) is one of two possible methods for performing this necessary translation. In this process, the current address needing translation is compared to a range of addresses stored in BAT registers. If the current address is found to be within this range, the BAT circuitry will provide an indication that the BAT circuitry is capable of providing the necessary address translation. If the address is not within this range, the BAT circuitry cannot perform the translation and a secondary method of translation must be employed.
The determination of whether the BAT circuit can provide a translation is made by referencing two fields within a register in the BAT circuitry. The first field within the register is for the starting address of the block for which this BAT circuit is providing a translation. The second field within the register is for the length of the block for which the BAT circuit is providing a translation. An example of valid block lengths are illustrated in Table 1.
TABLE 1 __________________________________________________________________________ Block Mask Bits and Segment Size for BAT Effective Page Index Bits Block Mask Bits BLK 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 SIZE 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 9 0 1 2 3 4 5 6 7 8 9 __________________________________________________________________________ 128K * * * * * * * * * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 256K * * * * * * * * * * * * * * X 0 0 0 0 0 0 0 0 0 0 1 512K * * * * * * * * * * * * * X X 0 0 0 0 0 0 0 0 0 1 1 1M * * * * * * * * * * * * X X X 0 0 0 0 0 0 0 0 1 1 1 2M * * * * * * * * * * * X X X X 0 0 0 0 0 0 0 1 1 1 1 4M * * * * * * * * * * X X X X X 0 0 0 0 0 0 1 1 1 1 1 8M * * * * * * * * * X X X X X X 0 0 0 0 0 1 1 1 1 1 1 16M * * * * * * * * X X X X X X X 0 0 0 0 1 1 1 1 1 1 1 32M * * * * * * * X X X X X X X X 0 0 0 1 1 1 1 1 1 1 1 64M * * * * * * X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1 128M * * * * * X X X X X X X X X X 0 1 1 1 1 1 1 1 1 1 1 256M * * * * X X X X X X X X X X X 1 1 1 1 1 1 1 1 1 1 1 __________________________________________________________________________
The circuit logic required to determine if an address is within a specified address range (starting at address 2.sup.m and ending on address {2.sup.n -1} where m and n are positive integers and m&lt;n) is well known and straightforward. For example, if it were necessary to determine whether the address B0:7! (with B0 being the most-significant bit) was within the eight bit address range from addresses 64 to 127, it is necessary only to compare the bit B1! to a logic "1" and bit B0! to a logic "0". Based on the binary representations of each address in this address range, it can be seen that this comparison would generate a match for all addresses between 64 and 127, inclusive.
The binary representation for numbers is particularly convenient for this address matching task. However, if the traditional binary representation of numbers is not used, the nature of the problem changes considerably. In certain microprocessor designs, many numbers and busses are represented in a signaling format described as 2B format. This signaling format encodes data into groups of two bits represented by four signals with only one out of the four signals active at any time. From this description, we can see that the numbers zero through three would be represented as "1000", "0100", "0010" and "0001", respectively. The use of 2B formatting of signals adds considerable complexity to the logic that determines whether an address is within a predefined range. Therefore, the need exists for a method and apparatus to determine whether a current address is within a range of addresses when the addresses are represented by a number of binary logic bits in a format such as the 2B format.